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Modern CMOS technology has reached a critical dimension (CD) of less than 45 nm, bringing about difficulties in perfectly transferring pattern on to silicon wafers in the process of lithography. Optical proximity correction (OPC) is thus introduced so as to improve print image fidelity. Conventional OPC aims at minimizing edge placement error (EPE), without considerations of post-lithography circuit performances. We propose a novel timing performance oriented OPC approach that passes estimated timing performance as feedback to OPC engine. Our method furthermore simplifies mask complexity by using simple rectangular tuning of transistor geometries, and reduces mask cost significantly. Our result outperforms conventional EPE-OPC by 5% improvement in timing accuracy and 30% reduction in mask size.