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Failure rate estimation of each process layer using critical area analysis and failing bit results

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10 Author(s)
Matsumoto, C. ; Production Eng. Res. Lab., Hitachi, Ltd., Yokohama, Japan ; Hamamura, Y. ; Chida, T. ; Tsunoda, Y.
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We propose a novel method by which to accurately estimate the failure rate of each process layer on a wafer-by-wafer basis. In this method, we use the failing bit data and the results of critical area analysis (CAA) of each failing bit signature (FBS). We formulate the estimation as a linear programming model and convert the failure rate of each FBS to the failure rate of each process layer. A comparison of the failure rate estimated using this method and that obtained by test structure analysis reveals good agreement and the total estimation error of all process layers are within several percent. We also improved a legacy yield management system by implementing this estimation method. This system is used for failure analysis during semiconductor manufacturing. We show two case studies for 65 nm and 45 nm technology node products.

Published in:

Advanced Semiconductor Manufacturing Conference (ASMC), 2010 IEEE/SEMI

Date of Conference:

11-13 July 2010