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32nm yield learning using efficient parallel-test structures

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4 Author(s)
Muthu Karthikeyan ; IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, NY 12533 USA ; Louis Medina ; Ernesto Shiling ; David Kiesling

The continuing rise in the number and complexity of test structures required to characterize every new technology generation demands at least a commensurate increase in test throughput. At IBM, various 32nm yield test structures are being tested on a functional test platform using customized Source Measurement Units (SMU) that allow parallel current measurement on up to 100 pins. This novel method improves test throughput as much as 9X over traditional parametric testing while offering current measurement resolution down to 100 fA. The test structures described herein help accelerate yield learning by enabling characterization of yield-loss mechanisms and rapid evaluation of yield improvement actions.

Published in:

2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

Date of Conference:

11-13 July 2010