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In this paper, we describe a novel scheme for radiation hardening of high performance pipelined architectures and data paths. The proposed technique uses a local ground bus decoupled from the global ground using an additional pull down device, to detect a transient error. Combining the detector output with duplicated pipeline registers enables an instruction execution through the data path to be repeated as soon as the error is detected. The detector outputs from various stages in a pipelined data path are manipulated to maintain correctness of data in the event of a transient error detection and corresponding instruction roll back. The proposed technique is extremely effective for errors of different pulse widths and comes without the extra cost of error checking codes, watch dog processors and logic core duplication as used by other techniques in literature. Our scheme provides 100% radiation hardening over all process corners with only 9.7% and 21.73% area and power overhead respectively with the delay overhead being masked out by the pipeline stages used in modern high performance data path architectures.