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Design of an Automatic Target Recognition algorithm on the IBM Cell Broadband Engine

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2 Author(s)
Weijia Che ; Faculty of Computer Science and Engineering, Arizona State University, Tempe, AZ 85287 ; Karam S. Chatha

The paper presents the design of an Automatic Target Recognition (ATR) algorithm on the IBM Cell Broadband Engine (Cell BE). The implementation utilizes several optimizations that exploit both the specific algorithm constructs of the ATR and the architectural features of the Cell processor. We discuss a total of 8 optimizations and present performance improvements achieved by their application. The latency of the Cell BE implementation of the ATR algorithm is 0.070 seconds on the Sony PlayStation3 (PS3) platform. The achieved performance is more than 25 times faster than the fully optimized PowerPC implementation and almost 20 times faster than our best efforts on a Pentium4 CPU.

Published in:

ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors

Date of Conference:

7-9 July 2010