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Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion

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2 Author(s)
Akl, C.J. ; Center for Adv. Comput. Studies (CACS), Univ. of Louisiana at Lafayette, Lafayette, LA, USA ; Bayoumi, M.A.

A simple yet effective technique that aims at reducing the energy and latency overheads incurred during the wakeup period of MTCMOS circuits is presented in this paper. One or more high-Vth keepers are inserted in MTCMOS combinational logic to reduce the metastability time that causes excessive short circuit current during mode transition and to minimize spurious glitches at internal circuit nodes. Employing the proposed keeper insertion technique in a 16-bit MTCMOS adder, up to 17.5% average wakeup energy and 54.6% wakeup latency reductions are achieved with negligible runtime power and latency overheads, while maintaining the standby energy efficiency of the original MTCMOS design.

Published in:

Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on

Date of Conference:

11-13 Aug. 2008