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With the technology moving into the deep sub-100 nm region, the increase of leakage power consumption necessitates more aggressive power reduction techniques. Power gating is a promising technique. Our research emphasizes the virtual ground voltage (VVG) as the key to make critical design trade-offs for power gating. We develop an accurate model to estimate the dynamic VVG value of a circuit block as a function of time after its ground is gated. Experimental results show that the model has less than 1% average error compared with HSPICE results. The CAD tool implemented based on the model has a 100 times speedup over HSPICE.
Date of Conference: 11-13 Aug. 2008