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Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators

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6 Author(s)
Niiyama, T. ; Univ. of Tokyo, Tokyo, Japan ; Zhe Piao ; Ishida, K. ; Murakata, M.
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In order to explore the feasibility of the large scale subthreshold logic circuits and to clarify the lower limit of supply voltage (VDD) for logic circuits, the dependence of minimum operating voltage (VDDmin) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90-nm CMOS ring oscillators (RO's). The measured average VDDmin of inverter RO's increased from 90 mV to 343 mV when the number of RO stages increased from 11 to 1 Mega, which indicates the difficulty of the VDD scaling in the large scale subthreshold logic circuits. The dependence of VDDmin on the number of stages is calculated with the subthreshold current model with random threshold voltage (VTH) variations and compared with the measured results, which confirm the tendency of the measurement.

Published in:

Low Power Electronics and Design (ISLPED), 2008 ACM/IEEE International Symposium on

Date of Conference:

11-13 Aug. 2008