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This letter presents a high-performance architecture of a novel first-order polynomial convolution interpolation for digital image scaling. A better quality of interpolation is achieved by using higher order model that requires complex computations. The kernel of the proposed method is built up of first-order polynomials and approximates the ideal sinc-function in the interval [-2, 2]. The proposed architecture reduces the computational complexity of generating weighting coefficients and provides a simple hardware architecture design and low computation cost, and easily meets real-time requirements. The architecture is implemented on the Virtex-II FPGA, and the high-performance very-large-scale integration architecture has been successfully designed and implemented with the TSMC 0.13 μm standard cell library. The simulation results indicate that the interpolation quality of the proposed architecture is mostly better than cubic convolution interpolations, and is able to process varying-ratio image scaling for high-definition television in real-time.
Circuits and Systems for Video Technology, IEEE Transactions on (Volume:20 , Issue: 9 )
Date of Publication: Sept. 2010