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Design of an ASIC architecture for high speed fractal image compression

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4 Author(s)
F. Ancarani ; Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy ; D. De Gloria ; M. Olivieri ; C. Stazzone

We report the results of the design and performance evaluation of an ASIC dedicated to fractal image compression. The ASIC is to be hosted on a PC platform by means of an interface board connected to the PCI bus. The obtained speed-up is 300 times with respect to the direct execution of the compression algorithm on a 100 MHz Pentium platform. The ASIC has been synthesized from VHDL and totals 150000 transistors

Published in:

ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

Date of Conference:

23-27 Sep 1996