By Topic

A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Joshi, R. ; IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA ; Kanj, R. ; Keunwoo Kim ; Williams, R.
more authors

This paper presents a novel dynamic supply boosting technique for low voltage SRAMs at/beyond 65 nm PD/SOI technologies. For the first time the technique exploits the capacitive coupling effect in a floating-body PD/SOI device to dynamically boost the virtual array supply voltage during Read operation, thus improving the Read performance, Read/half-select stability, and Vmin. This enables significant reduction of the standby cell power and circuit active power in a single supply methodology. The performance and parametric yield improvements in the presence of variability are analyzed/validated using precise and fast Monte Carlo statistical circuit simulations with mixture importance sampling. Fabricated column-based 65nm PD/SOI SRAM circuits are confirmed with simulations and physical analysis and are shown to operate at 0.4 V. to 0.5V.

Published in:

Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on

Date of Conference:

27-29 Aug. 2007