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Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies

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3 Author(s)
Mukhopadhyay, S. ; IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA ; Keunwoo Kim ; Ching-Te Chuang

This paper demonstrates viable device design options for low-leakage and robust SRAM in sub-50nm FD/SOI technology. We explore the possibilities of reducing the body-doping of FD/SOI devices with proper tuning of back-gate bias or gate workfunction to achieve a given leakage target. The reduction of body-doping density helps reduce the effect of the random dopant fluctuation (RDF), while the Vt and leakage are controlled using the back-gate bias. Our analysis show that, body-doping reduction combined with back-gate biasing is the most efficient FD/SOI device design for low-leakage and robust SRAM.

Published in:

Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on

Date of Conference:

27-29 Aug. 2007