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Evaluating design tradeoffs in on-chip power management for CMPs

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3 Author(s)
Sharkey, J. ; IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA ; Buyuktosunoglu, A. ; Bose, P.

In light of the recent shift towards multi-core processor designs, dynamic power-management techniques that were designed for single-core microprocessors must be augmented with larger chip-level control. In this paper, we explore the design-tradeoffs associated with CMP power management solutions in a full-system simulation environment. We show that global power management solutions outperform solutions that locally manage power per-core. We then show that global power management is most effective at finer granularities that allow it to adapt to changing workload behavior and thus conclude that on-chip hardware solutions for CMP power management are an important consideration for future CMP microprocessors.

Published in:

Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on

Date of Conference:

27-29 Aug. 2007