Cart (Loading....) | Create Account
Close category search window

Timing-driven row-based power gating

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
6 Author(s)
Sathanur, A. ; Politec. di Torino, Turin, Italy ; Pullini, A. ; Benini, L. ; Macii, A.
more authors

In this paper we focus on leakage reduction through automatic insertion of sleep transistors using a row-based granularity. In particular, we tackle here the two main issues involved in this methodology: (i) Clustering and (ii) the interfacing of power-gated and non power-gated regions within the same block. The clustering algorithm automatically selects an optimal subset of rows that can be power-gated with a tightly controlled delay overhead. We then address the issue of interfacing different gated regions and propose a novel technique to address this issue with minimal area and power penalty. Our approach is compatible with state-of-the art logic and physical synthesis flows and it does not significantly impact design closure. We achieve leakage power reductions as high as 89% for a set of standard benchmarks, with minimum timing and area overhead.

Published in:

Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on

Date of Conference:

27-29 Aug. 2007

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.