Skip to Main Content
In this paper, we propose a novel gate sizing approach for circuit optimization in the presence of scarce information about the distributions of the process variations. The proposed methodology relies upon the concepts of utility theory and risk minimization for multimetric optimization of delay, dynamic power, leakage power, and crosstalk noise, via gate sizing. A deterministic linear equivalent model from a fundamentally stochastic design optimization problem, ensuring high levels of expected utility and significant speedup in the optimization process for large circuits is derived in this work. Experimental results indicate that the proposed algorithm is efficient in terms of optimization results with multifold speedup in execution times compared to the traditional approaches.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:19 , Issue: 9 )
Date of Publication: Sept. 2011