Skip to Main Content
In this paper we propose an accurate and predictive interconnect density function (PIDF) for very deep submicrometer (VDSM) integrated circuits and nano-systems using continuous stochastic functions. PIDF is the core of an interconnect-centric prediction engine, named ICPEn, which gets its input parameters from the design flow of conventional chips, VDSM ICs, and/or nano-systems. Initially layout information is not necessary for PIDF to function properly. In average, we show that PIDF presents at least 10 times more accuracy than previous works using the real data. Moreover, PIDF enables ICPEn to predict the power, the delay, and the crosstalk. Credibility and accuracy of the last three predictions are proven using several standard ISCAS benchmarks and layouts. Using PIDF we extract a safe operating space (SOS) needed for the interconnect-centric design flow where the delay and the power boundary compliance are essential needs in any early design stages of ultra dense ICs. Based on the use of central limit theorem, the other novelty of PIDF is that the statistical distribution employed for the prediction of interconnect density function tends toward a continuous normal distribution which minimizes the residual error of the prediction and verifies the effectiveness of PIDF.