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This paper proposes a 3-GHz built-in jitter measurement (BIJM) circuit to measure clock jitter on high-speed transceivers and system-on-chip (SoC) systems. The proposed BIJM circuit adopts a high timing resolution and self-calibration techniques. To eliminate process variation effects in 3 GHz systems, this study proposes an auto-calibration technique for the self-refereed circuit and other calibration techniques for the time amplifier (TA) and vernier ring oscillator (VRO), respectively. These calibration techniques can reduce the timing resolution variation of the vernier ring oscillator and the gain variation of the TA by 66% and 65%, respectively. This reduces the timing resolution variation of BIJM by 60%. Because the vernier ring oscillator and time amplifier achieve a small timing resolution, the BIJM circuit does not need an additional jitter-free reference signal using the self-refereed circuit. This study fabricated the BIJM circuit using the UMC 90-nm CMOS process. The BIJM circuit has a power consumption measuring 11.4 mW, and its core area is 120 μm × 320 μm. The BIJM circuit measured the Gaussian distribution jitter at a 1.8 ps timing resolution with a 3-GHz input clock frequency.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:19 , Issue: 8 )
Date of Publication: Aug. 2011