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Reliability of thin seamless package with embedded high-pin-count LSI chip

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5 Author(s)
Kentaro Mori ; Device Platforms Research Laboratories, NEC Corporation 1120 Shimokuzawa, Sagamihara, 229-1198, Japan ; Katsumi Kikuchi ; Daisuke Ohshima ; Yoshiki Nakashima
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We have previously reported the technology for embedding a 1500-pin microprocessor chip in a thin LSI package using a rigid Cu plate. The reliabilities of this seamless package with the direct interconnection between the LSI chip and substrate wiring have now been evaluated at the package and board levels. The package passed all the LSI function tests at the package level even after 2000 thermal cycles. The microstructure of the interconnect, evaluated using electron backscatter diffraction and transmission electron microscopy, showed a high interconnect reliability. The reliability at the board level was evaluated using the thermal cycles testing, the shadow-moiré method and strain gauge measurement with the package mounted on a system board. Thanks to the Cu plate, the warpage and strain characteristics are excellent, resulting in uniform stress distribution. Therefore, this seamless packaging technology is promising for the fabrication of thin, highly reliable LSI packages for replacing flip chip ball grid array packages.

Published in:

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

Date of Conference:

1-4 June 2010