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Design of Tamper-Resistant Registers for Multiple-Valued Cryptographic Processors

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4 Author(s)
Baba, Y. ; Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan ; Homma, N. ; Miyamoto, A. ; Aoki, T.

This paper presents the design of tamper-resistant registers for multiple-valued cryptographic processors. The voltage-mode and current-mode registers are proposed for hiding dependencies between power consumption and input data. For this purpose, the voltage-mode register activates any one of two flip-flops in a complementary style, and the current-mode register maintains the number of current signals independently of the input value. This paper also applies the two registers to RSA processors in Multiple-Valued Current-Mode Logic and evaluates the power characteristics by HSIM simulations using 90nm process technology. The result shows that the proposed designs can achieve constant power consumption with lower overhead in comparison with the conventional designs.

Published in:

Multiple-Valued Logic (ISMVL), 2010 40th IEEE International Symposium on

Date of Conference:

26-28 May 2010