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A slow-wave microstrip line (S-MSL) designed in 0.13 μm CMOS technology with a high-Q and a high dielectric constant is proposed in this letter. Grounded metal strips with two metal layers are located in zigzags in order to prevent penetration of the electric field into the silicon substrate. These metal strips equate the potentials of the ground planes and thus eliminate the parasitic coupled slotline mode without requiring additional air-bridges. Also, locating the ground planes in the SiO2 layers instead of on the top metal reduces the size of the gap between the signal line and ground planes relative to the conventional structure. This allows relaxation of the metal density rule of the CMOS processes. Measured results for the proposed S-MSL show that the relative permittivity is 25 and the quality factor ranges from 18 to 37.7 between 20 and 60 GHz. The wavelength of the measured 253 μm S-MSL is 4/λ at 60 GHz.