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A 60 GHz-Standard Compatible Programmable 50 GHz Phase-Locked Loop in 90 nm CMOS

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5 Author(s)
F. Barale ; Georgia Electronic Design Center (GEDC), School of Electrical and Computer Engineering, Georgia Institute of Technology, GA, USA ; P. Sen ; S. Sarkar ; S. Pinel
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This letter presents, for the first time, a 60 GHz four-channel standard compatible heterodyne frequency synthesizer solution with low-cost reference signal. The presented PLL features a dual-core varactor-based LC cross-coupled voltage-controlled oscillator (VCO). The measured phase noise is -80.1 dBc/Hz at 1 MHz offset, and it is limited by the phase noise of the reference signal. The measured output spectrum shows spur suppression higher than 32 dBc. Using the lowest reference frequency to date (27 MHz), the presented PLL is suitable for applications in low cost fully integrated multi-gigabit 60 GHz CMOS radio transceivers.

Published in:

IEEE Microwave and Wireless Components Letters  (Volume:20 ,  Issue: 7 )