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As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power, performance, and area has become crucially important. In this work, we develop accurate architecture-level on-chip router cost models using machine-learning-based regression techniques. Compared against existing models (e.g., ORION 2.0 and parametric models), our models reduce estimation error by up to 89% on average.