Referenced Items are not available for this document.
A fully bidirectional mixed-voltage input/output (I/O) buffer using a novel floating N-well circuit is presented. To provide appropriate gate voltages for output stage transistors, a dynamic gate bias generator without gate-oxide overstress effect is implemented. The proposed I/O also takes advantage of a novel gate-tracking circuit and a PAD voltage detector by means of eliminating the leakage current such that the compatibility among all subcircuits is ensured. Our design is proved on silicon using 0.18 μm CMOS process that when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, the maximum data rate is found to be 80/80/125/100/80 MHz, respectively, with a given capacitive load of 10 pF.
Published in:
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
(Volume:19
,
Issue:
8
)
Date of Publication: Aug. 2011
- Page(s):
- 1481 - 1485
- ISSN :
- 1063-8210
- INSPEC Accession Number:
- 12186209
- Digital Object Identifier :
- 10.1109/TVLSI.2010.2049668
- Product Type:
- Journals & Magazines
- Date of Publication :
- 24 May 2010
- Date of Current Version :
- 25 July 2011
- Issue Date :
- Aug. 2011
- Sponsored by :
- IEEE Circuits and Systems Society
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
