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Advancing NASA's on-board processing capabilities with reconfigurable FPGA technologies: Opportunities & implications

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1 Author(s)
Paula J. Pingree ; Jet Propulsion Laboratory, California Institute of Technology, Pasadena, USA

Future NASA missions will require measurements from high data rate instruments. Recent internal studies at NASA's Jet Propulsion Laboratory (JPL) estimate approximately 1-5 Terabytes per day of raw data (uncompressed) are expected. Implementations of on-board processing algorithms to perform lossless data reduction are required to drastically reduce data volumes to within the downlink capabilities of the spacecraft and existing ground stations. Reconfigurable Field Programmable Gate Arrays (FPGAs) can include embedded processors thereby providing a flexible hardware and software co-design architecture to meet the on-board processing challenges of these missions while reducing the critical spacecraft resources of mass and volume of earlier generation flight-qualified single board computers such as the Rad750. Reconfigurable FPGAs offer unique advantages over one-time programmable (OTP) FPGAs with the flexibility to update processing algorithms as needed during the development cycle and even post-launch. So what's the downside? The space radiation environment poses challenges to these devices and in general, new technology introduces risk, either real or perceived, to one-of-a-kind space missions that cost hundreds of millions up to $1 billion. This talk will highlight both the opportunities and implications of advancing NASA's future on-board processing capabilities with reconfigurable FPGA technologies.

Published in:

Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 IEEE International Symposium on

Date of Conference:

19-23 April 2010