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Emerging high-speed network systems are capable of transporting and delivering data at rates faster than hardware and software components can economically process them. The result is data overflow in which performance information that is critical for effective network system monitoring and management may be lost, thereby leaving the system vulnerable to quality of service degradation and the service provider unable to meet customer service level agreements. Service providers seek a solution to this problem that minimizes the amount of high-speed, high-cost electronics required to comprehensively recognize such information. This paper addresses the challenge of surmounting data overflow problems in the collection of information by introducing a new procedure to transform finite state recognizers into new machines that can recognize bit-level information as it passes a monitoring point while operating slower than bit-rate for implementation in reconfigurable hardware, such as RAM and Field Programmable Gate Arrays. This is accomplished by mapping N-bit sets from the input stream into new symbols that can be processed at rate 1/N while also generating N-bit output symbols. The process is illustrated by implementation examples, and a time versus space tradeoff analysis is presented.