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Implementation of processor cells for array algorithms on FPGAs

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2 Author(s)
Vassanyi, I. ; KFKI Res. Inst. for Meas. & Comput. Tech., Budapest, Hungary ; Erenyi, I.

Recent advances in FPGA technology offer a suitable environment for massively parallel, fine-grain array architectures. The paper gives geometric criteria for an optimal “jigsaw tessellated” processor cell, and cost function for cell placement. The paper demonstrates the use of FPGA-based processor arrays by the implementation results of two cellular image processing algorithms. The outlined concepts are being implemented in a placement-routing tool

Published in:

EUROMICRO 96. Beyond 2000: Hardware and Software Design Strategies., Proceedings of the 22nd EUROMICRO Conference

Date of Conference:

2-5 Sep 1996