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As the technology scales down to nanometer regime, interconnect delay is more dominant than gate delay. Many approaches primarily concentrated to find the interconnect delay rather than gate delay so that one can increase the speed of the circuit by simply decreasing the interconnect delay. Several approaches have been proposed to find the interconnect delay accurately and efficiently. By considering the impulse responses of linear circuit as a Probability Distribution Function (PDF), Elmore first estimated the value of interconnect delay. Several approaches have been proposed after Elmore Delay metric like PRIMO, AWE, h-gamma, WED, D2M etc. and are proven to be more accurate than Elmore delay metric. But they suffer from computational complexity when using in total IC design processes. From then onwards many researchers are trying to get a simplified and accurate expressions for interconnect delay by using different techniques and by considering different Probability Distribution Functions (PDF) as their impulse responses. Our work presents a closed form formula for on-chip VLSI RC interconnects delay. Delay metric is obtained by matching circuit moments to the Beta distribution function. The delay metric can be easily implemented for both step and ramp inputs by using a single look-up table. By simply calculating first two circuit moments we can find the interconnect delay of the linear circuit and the computation is also less when compared to other approaches which involve greater computational complexity. As impulse response of the linear circuit matches, in most of the cases, with the Probability Distribution Function (PDF) of Beta Distribution, this method of finding interconnect delay can be used in many linear circuits. The accuracy of our model is justified with the results compared with that of SPICE simulations and the models that have already being proposed with other probability distribution function.