Referenced Items are not available for this document.
Superscalar processor developers are creatively leveraging best-in-class design verification tools to meet narrow market windows. Accelerated simulation is especially useful owing to its flexibility for verifying at many points during the design cycle. A unique “verification backplane” makes continuous verification at any level(s) of abstraction available to each design team member throughout the design cycle
Published in:
Design Automation Conference Proceedings 1996, 33rd
Date of Conference: 3-7 Jun, 1996
- Page(s):
- 311 - 314
- Meeting Date :
- 03 Jun 1996-07 Jun 1996
- ISSN :
- 0738-100X
- Print ISBN:
- 0-7803-3294-6
- INSPEC Accession Number:
- 5341689
- Conference Location :
- Las Vegas, NV
- Digital Object Identifier :
- 10.1109/DAC.1996.545592
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
