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Performance improvement of the memory hierarchy of RISC-systems by application of 3-D technology

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4 Author(s)
Kleiner, Michael B. ; Corp. Res. & Dev., Siemens AG, Munich, Germany ; Kuhn, Stefan A. ; Ramm, P. ; Weber, W.

In this paper, the performance of the memory hierarchy of RISC-systems for implementations employing three-dimensional (3-D) technology is investigated. Relating to RISC-systems, 3-D technology enables the integration of multiple chip-layers of memory together with the processor in one 3-D IC. In a first step, the second-level cache can be realized in one 3-D IC with processor and first-level cache. This results in a considerable reduction of the hit time of the second-level cache due to a decreased access time and a larger allowable bus-width to the second-level cache. In a further step, the main memory can be integrated which relieves restrictions with respect to the bus-width to main memory. The use of 3-D technology for system implementation is observed to have a significant impact on the optimum design and performance of the memory hierarchy, Based on an analytical model, performance improvements on the order of 20% to 25% in terms of the average time per instruction are evaluated for implementations employing 3-D technology over conventional ones. It is concluded that 3-D technology is very attractive for future RISC-system generations

Published in:

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on  (Volume:19 ,  Issue: 4 )

Date of Publication:

Nov 1996

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