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Although plastic packaging has successfully replaced ceramic and metal packages for many high reliability electronic packaging applications (e.g. military and aerospace), hermetically sealed ceramic packages are still the dominant technology for large power devices, such as the thyristors and diodes used in high voltage DC (HVDC) power transmission. With increasing energy requirements of growing economies, the demand for higher operating currents is driving suppliers to use larger diameter silicon devices, therefore requiring bigger and more expensive packages. A switch to polymer packaging in such applications has the potential to provide robust and light weight components at a lower cost. A Finite Element Analysis (FEA) based study aimed at optimising the electrical performance of a polymeric package for such power semiconductors is described in this paper. From the FEA simulations carried out, it was observed that one critical region where the electrical stresses tend to be high, and long-term failure may therefore occur, is in the contact region between the polymer housing and the metal inserts (flanges) which attach the housing to the copper pole pieces of the device. Different design features for the insert edge were studied in order to investigate their influence and to reduce the peak electrical field (E-field) in the critical region. The results showed that the E-field around the contact region decreased as the radii of curvature of the insert ends was increased. A comparison of the E-field magnitude for different insert designs also showed it to be lower around an elliptical insert end compared to circular and straight flange designs. Changes in the depth to which the flange protrudes inside the housing also had a significant effect in the electrical field magnitude in the contact region, whilst variation of other housing design parameters, such as the package thickness and the location of the insert relative to the housing periphery, did not cause the ele- ctric field to change significantly.