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Common architecture for decoding turbo and LDPC codes

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3 Author(s)
T. S. V. Gautham ; Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai, India 600036 ; Andrew Thangaraj ; Devendra Jalihal

Turbo codes and Low Density Parity Check (LDPC) codes have been shown to be practical codes that can approach Shannon capacity in several communication systems. In terms of performance and implementation complexity, LDPC codes and turbo codes are highly comparable, especially at coding rates around 1/2. In many recent wireless standards such as 3GPP LTE and WiMax, both turbo and LDPC codes have been recommended at the encoder. However, the decoder for turbo codes involves trellises and the BCJR algorithm, while the decoder for LDPC codes uses sparse graphs and the message passing algorithm. Therefore, in several implementations, a designer is forced to implement either the turbo decoder or the LDPC decoder. The main idea behind this work is to enable the implementation of both decoders using a common architecture. We view the constituent convolutional code in a turbo code as a block code, and construct a sparse parity check matrix for it. Then, the sparse matrix and the associated bipartite graph are used for decoding the convolutional code by soft message passing algorithms. Simulation results show a manageable degradation in performance with a reduction in complexity.

Published in:

Communications (NCC), 2010 National Conference on

Date of Conference:

29-31 Jan. 2010