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3D 65nm CMOS with 320°C microwave dopant activation

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15 Author(s)
Lee, Yao-Jen ; Nat. Nano Device Labs., Hsinchu, Taiwan ; Yu-Lun Lu ; Fu-Kuo Hsueh ; Kuo-Chin Huang
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For the first time, CMOS TFTs of 65 nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P31 for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.

Published in:

Electron Devices Meeting (IEDM), 2009 IEEE International

Date of Conference:

7-9 Dec. 2009

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