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Cycle time reduction is crucial for semiconductor wafer fabrication companies to maintain competitive advantages as the semiconductor industry is becoming more dynamic and changing faster. According to Little's Law, while maintaining the same throughput level, the reduction in Work-in-Process (WIP) will result in cycle time reduction. On one hand, the existing queueing models for predicting the WIP of tool sets in wafer fabrication facilities (fab) have limitations in real settings. On the other hand, little research has been done to predict the WIP of tool sets with tool dedication and waiting time constraint so as to control the corresponding WIP levels of various tool sets to reduce cycle time without affecting throughput. This study aims to fill the gap by proposing a manufacturing intelligence (MI) approach based on neural networks (NNs) to exploit the value of the wealthy production data and tool data for predicting the WIP levels of the tool sets for cycle time reduction. To validate this approach, empirical data were collected and analyzed in a leading semiconductor company. The comparison results have shown practical viability of this approach. Furthermore, the proposed approach can identify and improve the critical input factors for reducing the WIP to reduce cycle time in a fab.