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Analysis and Design of an Ultralow-Power CMOS Relaxation Oscillator

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1 Author(s)
Urs Denier ; austriamicrosystems Switzerland AG, Rapperswil, Switzerland

This paper presents the design of a low-voltage ultralow-power relaxation oscillator without external components. The application field for this oscillator is the clock generation of low-power wake-up functions for battery-operated systems. A detailed analysis of the oscillator, including the temperature performance, is derived and verified with experimental results. The oscillator operates at a typical frequency of 3.3 kHz and consumes 11 nW from a 1-V supply at room temperature, and a temperature drift of less than 500 ppm/°C is achieved over the temperature range of -20°C to 80°C. An efficient design implementation has resulted in a cell area of 0.1 mm2 in a standard 0.35- μm digital CMOS technology.

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IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:57 ,  Issue: 8 )