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This paper presents the system level design of a novel multi-bit Sigma-Delta (ΣΔ) ADC architecture that replaces the flash quantizer and mismatch corrected multi-bit DAC of a ΣΔ modulator by an integrating quantizer and a Pulse-Width Modulated DAC. This converter achieves the resolution of a multi-bit design using single-bit circuitry. The quantizer of this modulator is similar to a classical Dual-Slope integrating converter, but the charge residue in the integrator at the end of each conversion cycle is stored for the next conversion, providing first order noise shaping. As an example, the system level performance of a second-order multi-bit ???? ADC using this new architecture has been evaluated. Also, circuit level specifications have been established, considering the most critical circuit non-idealities. The behavioral simulation results show that the ADC could achieve an ENOB = 13 bits in a signal bandwidth of 2 MHz using conventional CMOS technology, which could be suitable for wireless communication standards.