By Topic

A double-sampled hybrid CT/DT SMASH ΣΔ modulator for wideband applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Mohammad Hossein Maghami ; Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran ; Mohammad Yavari

This paper presents a novel hybrid continuous-time (CT) and discrete-time (DT) sturdy multi-stage noise shaping (SMASH) ΣΔ modulator architecture. The double-sampling technique is employed in the DT second stage modulator to reduce the power consumption of the overall modulator. A flat and unity STFs are used in the first and second stage modulators, respectively, to reduce the output swing of the analog building blocks without influencing the inherent anti-aliasing behavior of the first stage CT modulator. As a design example, the proposed SMASH 2-2 modulator is designed in a 90 nm CMOS technology with 1 V power supply. HSPICE simulation results show a signal-to-noise plus distortion ratio (SNDR) of 80.4 dB in 12.5 MHz bandwidth with 17 mW power consumption while operating at 200 MHz sampling frequency.

Published in:

Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on

Date of Conference:

13-16 Dec. 2009