Referenced Items are not available for this document.
This paper presents a novel ΣΔ-modified MASH architecture (MMA) for a CMOS imager. This architecture makes use of a 1st-order incremental continuous-time sigma-delta modulator with 1.5-bit internal quantizer. It shows key benefits regarding efficient decimation and reduced circuit complexity compared to conventional ΣΔ-architectures. Theory of operation, impact of non-idealities, implementation issues and benefits of the new architecture are depicted. The implementation of the MMA in an 180nm CMOS-Process and simulation results are presented.
Published in:
Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on
Date of Conference: 13-16 Dec. 2009
- Page(s):
- 33 - 36
- E-ISBN :
- 978-1-4244-5091-6
- Print ISBN:
- 978-1-4244-5090-9
- INSPEC Accession Number:
- 11142093
- Conference Location :
- Yasmine Hammamet
- Digital Object Identifier :
- 10.1109/ICECS.2009.5410946
- Product Type:
- Conference Publications
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