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In this paper, various aspects related to leakage power analysis (LPA) attacks to cryptographic circuits are discussed. These attack aim at recovering the secret key through measurements of chip static (leakage) power, and are a serious threat to the information security of cryptographic circuits in sub-100 nm CMOS technologies. A theoretical analysis of LPA attacks is developed to predict the result of practical attacks. In particular, a closed-form expression is provided for the correlation coefficient between the estimated and measured leakage as a function of the parameters related to the attack. This permits to gain an insight into the fundamental mechanisms involved in LPA attacks. Since LPA attacks are potentially sensitive to threshold voltage variations, the impact of process variations is also analyzed in detail. Results show that LPA attacks are expected to be robust against process variations also in the next process generations. Assumptions and results are finally validated through simulations on a 65-nm CMOS technology and measurements.