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Multiplier reduction trees that have a logarithmic logic depth generally exhibit poor regularity, in terms of how the gates are interconnected. Consequently, it is well known that partial-product reduction trees (PPRTs), such as Wallace, Dadda and TDM, are very difficult to lay out in a custom design flow. However, our previously proposed HPM scheme enabled the implementation of a PPRT that consistently uses regular interconnect patterns, without sacrificing the performance originating from the logarithmic logic depth. The original HPM layout is perfectly regular, however, it has a PPRT in the shape of a wide triangle. We now propose a custom layout strategy for the HPM scheme that leads to rectangle-shaped PPRTs that are more straightforward to reconcile with the need for a rectangular multiplier footprint. The proposed layout strategy is implemented and evaluated for a 16-bit 90-nm design.