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A Scalable Memory-Based Reconfigurable Computing Framework for Nanoscale Crossbar

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2 Author(s)
Paul, S. ; Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA ; Bhunia, S.

Nanoscale molecular electronic devices amenable to bottom-up self-assembly into a crossbar structure have emerged as a promising candidate for future electronic systems. To address some of the design challenges in molecular crossbar, we propose “memory-based architecture for reconfigurable computing” (MBARC), where memory, instead of switch-based logic functions, is used as the computing element. MBARC leverages on the fact that regular and periodic structures of molecular crossbar are attractive for a dense memory design. The main idea in MBARC is to partition a logic circuit, store the partitions as multi-input-multi-output lookup tables in a memory array, and then, use a simple CMOS-based scheduler to evaluate the partitions in a topological time-multiplexed manner. Compared to existing reconfigurable nanocomputing models, the proposed memory-based computing has three major advantages: 1) it minimizes the requirement of programmable interconnects (PIs); 2) it minimizes the number of CMOS interfacing elements that are required for level restoration and cascading logic blocks; and 3) it can achieve higher defect tolerance through efficient use of redundancy. Simulation results for a set of ISCAS benchmarks show average improvement of 32% in area, 21% in delay, and 34% in energy per vector compared to the implementation of a nanoscale field-programmable gate array. Effectiveness of the framework is also studied for two large sequential circuits, namely, 2-D discrete cosine transform and eight-tap finite-impulse-response filter.

Published in:

Nanotechnology, IEEE Transactions on  (Volume:11 ,  Issue: 3 )