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An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC

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4 Author(s)
Xueyang Geng ; Department of Electrical and Computer Engineering, 200 Broun Hall, Auburn University, AL, USA ; Fa Foster Dai ; J. David Irwin ; Richard C. Jaeger

This paper presents a low power, ultrahigh-speed and high resolution SiGe DDS MMIC with 11-bit phase and 10-bit amplitude resolutions. Using more than twenty thousand transistors, including an 11-bit pipeline accumulator, a 6-bit coarse sine-weighted DAC and eight 3-bit fine sine-weighted DACs, the core area of the DDS is 3 × 2.5 mm2. The maximum clock frequency was measured at 8.6 GHz with a 4.2958 GHz output. The DDS consumes 4.8 W of power using a single 3.3 V power supply. It achieves the best reported phase and amplitude resolutions, as well as a leading power efficiency figure-of-merit (FOM) of 81.1 GHz·2SFDR/6/W in the mm-wave DDS design. The measured spurious-free-dynamic-range (SFDR) is approximately 45 dBc with a 4.2958 GHz Nyquist output, and 50 dBc with a 4.2 MHz output in the Nyquist band at the maximum clock frequency of 8.6 GHz. Under a 7.2 GHz clock input, the worst-case Nyquist band SFDR and narrow band SFDR are measured as 33 dBc and 42 dBc respectively. The measured phase noise with an output frequency of 1.57 GHz is - 118.55 dBc/Hz at a 10 kHz frequency offset with a 7.2 GHz clock input generated from an Agilent E8257D analog signal generator. All the measurements were taken with the chips bonded in a CLCC-52 package.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:45 ,  Issue: 2 )