By Topic

A 12-bit — 35-MS/s pipeline ADC with dynamic element matching correction for ILC/CALICE integrated read-out

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Rarbi Fatah ; LPSC, CNRS/IN2P3 Laboratory, Université de Grenoble ; Dzahini Daniel ; Gallin-Martel Laurent

A low power 12 bits analog to digital converter is a critical part of a fully integrated readout system for the next ILC ECAL. We present here a new design of 12-bit ADC up to 35-MS/s using a pipelined architecture in a CMOS 0.35 m process. The first front-end stage of 2.5 bits includes an efficient dynamic element matching scheme permitting to average its gain errors. The back-end converter is a set of seven 1.5 bit stages followed by a 3 bit full flash. The dynamic range covered is 2V. The analog part of the converter can be quickly (in a couple of s) switched to a standby mode that reduces the DC power dissipation. The size of this converters layout including the output pads is 1.4mm¿¿1.3mm, and the total power dissipation is only 45mW.

Published in:

2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC)

Date of Conference:

Oct. 24 2009-Nov. 1 2009