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A simple model that links MOSFET performance, in the form of intrinsic switch delay, to effective carrier velocity in the channel is developed and fitted to historical data. It is shown that nearly continuous carrier velocity increase, most recently via the introduction of process-induced strain, has been responsible for the device performance increase commensurately with dimensional scaling. The paper further examines channel material innovations that will be required in order to maintain continued commensurate scaling beyond what can be achieved with process-induced strain, and discusses some of the technological tradeoffs that will have to be faced for their introduction.
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