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Optimization of silicon technology for the IBM System z9

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15 Author(s)
Poindexter, D.J. ; IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, New York 12533, USA ; Stiffler, S.R. ; Wu, P.T. ; Agnello, P.D.
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IBM 90-nm silicon-on-insulator (SOI) technology was used for the key chips in the System z9™ processor chipset. Along with system design, optimization of some critical features of this technology enabled the z9™ to achieve double the system performance of the previous generation. These technology improvements included logic and SRAM FET optimization, mask fabrication, lithography and wafer processing, and interconnect technology. Reliability improvements such as SRAM optimization and burn-in reliability screen are also described.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:51 ,  Issue: 1.2 )