By Topic

Analysis and design of an interleaved series input parallel output ZVS forward converter

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Shin-Ju Chen ; Dept. of Electr. Eng., Kun-Shan Univ., Tainan, Taiwan ; Sung-Pei Yang ; Meng-Fu Cho

A novel interleaved series input parallel output ZVS forward converter (ISIPO ZVSFC) is proposed in this paper. The series input and parallel output architecture enables the converter cells to share the input voltage and output current equally. The interleaved operation diminishes the output current ripple in the output capacitor. That reduces the size of the output filter. By using active-clamp circuit and resonant circuit, the converter can achieve ZVS operation for all the main and auxiliary switches. The active-clamp circuit is also used to reset the energy stored in the leakage inductor to minimize the voltage spike on switching devices. All these features make the proposed converter suitable for dc-dc converters with high input voltage, high output current, high power and high efficiency applications. An experimental prototype with 400 V input and 24 V/480 W output is built to verify the theoretical analysis and the performance.

Published in:

Power Electronics and Drive Systems, 2009. PEDS 2009. International Conference on

Date of Conference:

2-5 Nov. 2009