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A Test Vector Compression/Decompression Scheme Based on Logic Operation between Adjacent Bits (LOBAB) Coding

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4 Author(s)
Huaguo Liang ; Sch. of Electron. Sci. & Appl. Phys., Hefei Univ. of Technol., Hefei, China ; Wenfa Zhan ; Qiang Luo ; Cuiyun Jiang

A new test vector compression/decompression scheme, namely a scheme of logic operation between adjacent bits (LOBAB) is presented, which is based on bitwise logic operation between itself and its previous bit. It turns all kinds of series including continuous series, such as a series of all 0s and all 1s, and reversal series, such as a series of 01 and 10, into series of all 0s by logic operation between adjacent bits. On one hand, the two kinds of series, continuous series and reversal series, are both taken into account, which decreases the number of division to the original test data. On the other hand, all series are turned into series of all 0s, which eases the process of encoding and decoding. Compared with other already known schemes this scheme has some characteristics, such as high compression ratio, easy control and implementation. The performance of the algorithm is mathematically analyzed and its merits are experimentally confirmed on the larger examples of the ISCAS89 benchmark circuits.

Published in:

Dependable Computing, 2009. PRDC '09. 15th IEEE Pacific Rim International Symposium on

Date of Conference:

16-18 Nov. 2009