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Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy

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5 Author(s)
Jianbo Dong ; Key Lab. of Comput. Syst., Chinese Acad. of Sci., Beijing, China ; Lei Zhang ; Yinhe Han ; Guihai Yan
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Thread-level redundancy in Chip Multiprocessors(TLR-CMP) is efficient for soft error tolerance. Process variation causes core-to-core (C2C) performance asymmetry across a chip, which should be taken into consideration for application scheduling. In this paper, two types of variations beyond C2C are introduced, i.e., inter-pair and intra-pair variation in TLR-CMP. Intra-pair performance asymmetry can affect the performance of applications differently. Based on the above observation, we firstly formalize the variation aware scheduling in TLR-CMP as a 0-1 programming problem,to maximize the system weighted throughput. An efficient scheduling algorithm, named IntraVarF&AppSen, is then proposed to tackle this problem, which can be proved to be optimal when the number of applications to be scheduled is equal to the number of core pairs. Simulation on a 64-core CMP shows 2.8%-4% improvement in weighted throughput when compared to prior VarF&AppIPC algorithm.

Published in:

Dependable Computing, 2009. PRDC '09. 15th IEEE Pacific Rim International Symposium on

Date of Conference:

16-18 Nov. 2009