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Reconfigurable processors provide a means to flexible and energy-aware computing. In this paper, we present a new scheme for runtime energy minimization (REMiS) as part of a dynamically recon-figurable processor that is exposed to run-time varying constraints like performance and footprint (i.e. amount of reconfigurable fabric). The scheme chooses an energy-minimizing set of so-called Special Instructions (considering leakage, dynamic, and reconfiguration energy) and then 'power-gates' a temporarily unused subset of the Special Instruction set. We provide a comprehensive evaluation for different technologies (ranging from 65 nm to 150 nm) and thereby show that our scheme is technology independent, i.e. it is beneficial for various technologies alike. By means of an H.264 video encoder we demonstrate that for certain performance constraints our scheme (applied to our in-house reconfigurable processor) achieves an allover energy saving of up to 40.8% (avg. 24.8%) compared to a performance-maximizing scheme. We also demonstrate that our scheme is equally beneficial to various other state-of-the-art reconfigurable processor architectures like Molen where it achieves energy savings of up to 48.7% (avg. 28.93%) at 65 nm. We have employed an H.264 encoder within this paper as an application in order to demonstrate the strengths of our scheme, since the H.264's complexity and run-time unpredictability present a challenging scenario for state-of-the-art architectures.
Date of Conference: 2-5 Nov. 2009