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Racetrack memory promises a novel storage-class memory with the low cost per bit of magnetic disk drives but the high performance and reliability of conventional solid state memories. Unlike conventional memories, the fundamental concept of racetrack memory (RM) is to store multiple data bits as many as 10 to 100 bits per access point, rather than the typical single bit per transistor. This is accomplished in racetrack memory by storing data bits in the form of domain walls in magnetic nanowires which are oriented either parallel to the surface or perpendicular to the surface of a silicon wafer. These distinct structures form "horizontal" and "vertical" racetrack memories. This paper discusses progress towards building a racetrack memory and the fundamental physics underlying it. In particular, the current and field controlled dynamical motion of magnetic domain walls in magnetic nanowires formed from permalloy and related materials are discussed.
Device Research Conference, 2009. DRC 2009
Date of Conference: 22-24 June 2009