An advanced layered MPP architecture for industrial imaging

The massively parallel hardware approach to computer vision is a relatively new area. The traditional approach uses a parallel general-purpose computer that runs software to take advantage of the parallel processors. The number of parallel processors has varied from two up to a processor per pixel, at least in theory. The proposed approach is ideologically different. This research advocates the processing to be accomplished in layers that are totally parallel, especially at the lower levels. This approach uses dedicated hardware architectures, as opposed to the general-purpose processor, which are customer-oriented and application specific in nature. The system is composed of a new image layer, local communicator layer, processing element layer, and a main control unit. The PE design is facilitated by the development of a CAD designer tool. The goals of this research are to reduce PE complexity, reduce communication bottlenecks, provide for higher speed and throughput, and provide accessibility to portability requirements. The issues that require consideration includes: speed, throughput, system flexibility, system tolerance, and portability. This is why it is critical to determine at what stage of the VLSI design the designer should start to consider these effects. This research proposes to solve the aforementioned problems, in addition to presenting the advantages of the application-specific massively parallel hardware architecture for image recognition systems. This paper presents the background and developments, the technical summary, recommended areas of application, and conclusion.